The design of an integrated circuit (IC) that includes transistors and capacitors requires the implant and diffusion of donor or acceptor atoms within oppositely doped regions such as a substrate, nWell, or pWell. While the intent of the design is to create a functional device, these diffusions also form parasitic diodes to the surrounding substrate or Well regions. In early CMOS IC designs, it was always expected that the p-type substrate or pWell regions of the IC would be biased to the lowest potential available on the IC, and that n-type substrate or nWell regions would be biased toward the highest potential on the IC. Under this assumption, any p+ diffusion with an n-type background (or n+ diffusion in a p-type background) parasitic diode would be reverse biased and would not impact circuit function beyond the addition of a depletion capacitance.
Increasingly, however, as new IC designs push to higher performance, and analog functions are incorporated into ICs, biasing of Well structures between the highest and lowest potentials available has become commonplace. In addition, modern process technologies allow the existence of both nWell and pWell along with substrate on a single IC. And, it has become common for ICs to contain many voltage domains on a single die with data communication between voltage domains. As a result of this increased IC complexity and processing capacity, the risk of unintentionally creating a forward biased parasitic diode between supply domains of an IC during physical design has greatly increased.
Traditional Design Rule Check (DRC) tools verify that a layout can be manufactured as designed. Traditional Layout vs. Schematic (LVS) tools extract the layout and compare it to the schematic, to ensure a one-to-one correlation. Although DRC and LVS tools may be used independently, they are commonly used in conjunction with each other. Typically, these tools are used iteratively, and the masks are not built until the requirements of both tools are satisfied. While these methods are good at checking the design for adherence to technology ground rules and the equivalence of an IC physical design to its schematics, the detection and analysis of parasitic diode structures that can cause functional problems has not been successfully addressed. Designers have been left to verify their designs using a combination of parasitic netlist extraction and circuit simulation to ascertain whether the circuits function properly over a wide range of static and dynamic power scenarios.
Current methods and devices require exacting and exhaustive input patterns, and a careful review of the results, both of which are performed manually and are thus subject to human error. As these methods are heavily dependent upon the completeness of the simulation pattern suite, an incomplete or inaccurate extraction process may omit or alter the function of parasitic devices within the design.
In many cases, the parasitic devices in question would not be extracted as true diodes unless they were manually identified by the designer prior to netlist extraction, which is virtually impossible, as these structures may be incorporated into the design inadvertently. As a result, the escape rate for parasitic forward biased diode structures in the physical design is unacceptably high. The costs of such a high escape rate are expensive redesigns, more frequent product failures, and longer times to market.